Many Integrated Circuits (ICs) require a high voltage to operate. Among such ICs are the so called non-volatile memory ICs, which include EPROMs, EEPROMs and Flash-EPROMs. For a non-volatile memory IC, a high voltage, generated either internally or provided externally, is needed in order to program or erase the memory transistors that are used to store data.
In recent years demand for integrating different classes of functions, which until recently required several different ICs to achieve, has arisen. Combining the functions performed by several ICs into a single IC requires the development of new transistor structures capable of operating under different biasing conditions. ICs containing both non-volatile memory devices, e.g. memory transistors and the supporting circuitry, as well as circuits performing a variety of analog and digital functions are currently available in the market. Furthermore, a new generation of ICs use embedded Flash-EPROM memory transistors to program or erase a programmable logic device formed within the same IC.
In most such ICs, one or more p-channel or n-channel MOS transistors are typically placed in the path that carries a high voltage to the memory transistors. MOS transistors are employed in the high voltage path to either pass the high voltage to or inhibit the high voltage from being applied to the memory transistor during a programming/erase cycle. When an n-channel MOS transistor is used to inhibit a positive high voltage from being applied to a memory transistor, it must be able to withstand the high voltage that is applied to its drain terminal without entering a gated-diode breakdown region.
FIG. 1 shows the biasing condition that an n-channel MOS transistor 10 experiences when it is used to block a high voltage 30 applied to its drain terminal 24. As can be seen from FIG. 1, gate terminal 22 and source terminal 26 of transistor 10 are connected to ground while a high voltage 30 is applied to the transistor drain terminal 24.
To prevent transistor 10 from entering the gated-diode breakdown region, the electric field near the interface between drain 14 and channel 18 must be reduced.
One method of reducing the electric field near the drain-channel interface is to raise the potential of gate 12. For example, in FIG. 2A voltage supply 40 is applied to raise the potential of gate terminal 22. FIG. 2B illustrates the effect of increasing the gate-to-source voltage V.sub.gs of n-channel MOS transistor 10 on the transistor gated-diode breakdown voltage characteristic. In FIG. 2B, the x-axis designates the drain-to-source voltage V.sub.ds and the y-axis designates the drain current I.sub.ds flowing through drain terminal 24. Three graphs of drain current as a function of drain voltage are shown in FIG. 2B, with each graph representing a different gate-to-source V.sub.gs voltage. As can be seen form FIG. 2B, as the magnitude of gate-to-source voltage V.sub.gs increases, the magnitude of gated-diode breakdown voltage BV also increases (i.e. BV3 has a greater magnitude than BV2.) However, the increase in the gate-to-source voltage V.sub.gs causes transistor 10 to turn on, rendering transistor 10 inoperable as a high voltage switching device.
Exposing a conventional p-channel or n-channel MOS transistor to a high voltage for an extended period of time leads to other undesirable effects. Most notably, a high electric field in a transistor channel region adjacent a drain causes electrons to be injected from the channel into the gate oxide. This phenomenon which is commonly known as the "hot electron effect" leads to many long-term problems, e.g. transistor performance degradation and reduced reliability. The high-voltage induced problems become more pronounced as transistor dimensions decrease.
Techniques developed to reduce the high electric field near the drain-channel interface in order to increase the gated-diode breakdown voltage and to reduce the hot electron effect typically modify the dopant concentration of the drain so as to create a more gradual and a reduced doping concentration at the drain-channel interface. Two such techniques, widely known in the art, are the Lightly Doped Drain (LDD) and the Double Diffused Drain (DDD).
FIG. 3 shows a prior art MOS transistor 30 which includes LDD regions 12, as described in "VLSI TECHNOLOGY", by S. M. Sze, published by McGraw-Hill International 1988, pages 482-483. The dopant concentration in n LDD regions 12 are several orders of magnitude smaller than those in n+ regions 14. The reduction in the electric field near the drain-channel region (or the source-channel region) stemming from the reduction in the dopant concentration near the drain-channel interface results in an increase in the gated-diode breakdown voltage for transistor 30.
A disadvantage of transistor 30 is that it requires extra masking and implant steps to form LDD regions 12.
FIG. 4 show a transistor 40 which includes DDD to lower the electric field and thereby increase the gated-diode breakdown voltage, as described in U.S. Pat. No. 4,851,360 issued to Haken et al. As shown in FIG. 4, both the source and the drain regions of transistor 40 include two diffusion regions 14 and 18. To form doubled diffused regions 14 and 18, a first mask is used to implant regions 14 with phosphorous. Thereafter, using the same mask, arsenic is implanted into the same region, subsequent to which transistor 20 is implant annealed. Because phosphorous atoms have a greater diffusivity than arsenic atoms, they diffuse laterally during the implant anneal process to form region 18 which has a lower dopant concentration than does adjacent region 14.
A disadvantage of transistor 40 is that DDD regions 14 increase the source/drain junction capacitances. The increase in the RC time constants, caused by the increase in source/drain junction capacitances leads to longer propagation delays and slower performance of circuits that use transistor 40.
Another disadvantage of transistor 40 is that it requires an extra implant step to form DDD regions 14.